Aldec Integrates OpenVera Assertions Support Into Riviera 2003.03
Henderson Nevada, April 14th, 2003 -- Aldec, Inc., a pioneer in mixed language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of Riviera 2003.03 with integrated support for OpenVera� Assertions (OVA). Riviera is based on Aldec’s industry-proven VHDL and Verilog mixed-language simulation technology used by ASIC and high-density FPGA designers for new generation system-on-chip designs. Riviera’s addition of OVA capabilities provides designers with a flexible debugging tool that can be used at any level of the design hierarchy, pinpointing problems the moment they appear and reducing the number of iterations required to deliver a flawless design.
Integrated Assertion-Based Verification
OpenVera Assertions is a high-level language that contains powerful declarative constructs for accurately capturing design specifications and is useful in both dynamic and formal verification environments. Riviera now includes OVA support in order to reduce the number of iterations required in the design verification process. Assertions provide designers with the ability to embed design checks directly into HDL design blocks and dynamically monitor the checks, guaranteeing correct behavior at all levels in the design hierarchy. As a result, the verification of a design with embedded assertions enables the designer to check all interfaces and verify the integrity of the design at all levels, without having to write complex protocol checking as part of the testbenches for each discrete HDL module.
“As designs continue to grow, the need to find advanced methods, such as assertions, in order to verify these designs becomes equally important. The support for OVA in Riviera 2003.03 adds this additional level of verification required for these larger, more complex designs,” stated Eric Seabrook, product marketing manager for Aldec. “Using assertions as part of the verification methodology is simply smarter than traditional methods alone.”
Reducing Debugging Time
By incorporating OVA into Riviera, Aldec’s customers are able to reduce the overall time it takes to debug their design. Riviera’s support of OVA gives designers:
- A more comprehensive verification and debug environment with fewer simulation cycles
- Full access to all variables describing the design state
- Access to all design errors, which are flagged earlier in the simulation cycle closer to the source of the problem
- More effective tests to exercise transactions, packets and sequences
- The ability to automate testbenches based on feedback from assertions and functional coverage
Benefit of Using Assertions
A designer creating HDL blocks can easily add OVA into the design and verify it at the system level. This integrated approach to incorporating assertions to check all levels of the design hierarchy allows the system verification engineer to focus on aspects of the system-level behavior, and at the same time receive error messages of any lower-level modules that might not meet the design specifications. All error messages are reported in Riviera’s console, complete with the error’s reference line number in the source file; design scope; and timeframe for the potential problems in the design block. Flexible ways of including assertion data in the design assure seamless integration with existing design management methods. The ability to blueprint the design up-front with rules makes outsourcing and future re-use much easier when the entire design is brought back together. Additionally, using assertions in parallel with a traditional testbench generates better verification results by improving the overall coverage with less effort.
“The design and verification community is driving the demand for OVA language-based product support in order to adopt an assertion-based verification methodology and increase productivity," said James Watts, OpenVera program manager at Synopsys, Inc. "Aldec’s announcement adds to the OVA momentum and marks growing EDA tool support for the language."
Future Implementation Based on Accellera Standards
Riviera actively supports languages standardized by Accellera, the electronics industry organization focused on language-based design standards. Aldec’s Riviera simulator supports OVA, which has been accepted as a donation towards the unified assertions within SystemVerilog 3.1. Aldec will implement support for SystemVerilog 3.1 assertions after Accellera finalizes the language specification.
Availability
Riviera 2003.03 is available today based on a floating, OS independent license that supports UNIX, Windows and Linux. It includes an industry-proven mixed VHDL and Verilog simulation engine that supports IEEE VHDL 1076-87/93, and Vital 2000 in addition to Verilog 1376-95 and 2001. Riviera 2003.03 includes built-in assertion support for OpenVera, as well as advanced debugging tools such as Code Coverage and Design Profiler. Riviera interfaces to other EDA tools via its PLI and VHPI function calls. Riviera is sold directly by Aldec in the U.S. and authorized international distributors. A FREE evaluation copy of Riviera, go to www.aldec.com.
About Aldec
Aldec, Inc., a 19-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs with its offices located around the globe. Continuous innovation, superior product quality and total commitment to customer service comprise the foundation of Aldec’s strategic objectives. Additional information about Aldec is available at http://www.aldec.com.
